Until recently, integrated circuits utilized primarily transistors with polysilicon gates and silicon dioxide or nitrided silicon dioxide gate dielectrics.
Complementary Metal-Oxide-Semiconductor (CMOS) transistors with high dielectric constant (hi-k) dielectrics and metal gates were introduced as technologies scaled to 28 nm and below to combat short channel effects and to improve performance of the highly scaled transistors. The hi-k dielectrics provide improved capacitive control of the transistor channel by avoiding an apparent increase in gate dielectric thickness due to depletion of carriers in the polysilicon grains near the gate dielectric interface.
A significant challenge with hi-k/metal gate transistors is achieving the optimum workfunction for the best transistor performance. The workfunction of the gate for p-channel metal-oxide-semiconductor (PMOS) transistors is preferably greater than about 4.8 eV and the workfunction for n-channel metal-oxide-semiconductor (NMOS) transistors is preferably less than about 4.3 eV.
Processing in conventional hi-k/metal gate manufacturing may be very complicated and expensive to achieve a different work function on NMOS and PMOS transistors. For example, NMOS transistors may have a different gate metal and or may have a different hi-k gate dielectric than PMOS transistors.
There are primarily four different process flows for forming hi-k/metal gate transistors: hi-k last replacement gate; hi-k first replacement gate; hi-k last gate first; and hi-k first gate last. In replacement gate transistor flows, conventional polysilicon gate transistors are formed first and then the polysilicon gate is removed and replaced with a metal gate. In gate first process flows, the metal gate transistors are formed similar to conventional polysilicon gate transistors but with a metal gate. In hi-k last process flows, a silicon dioxide dielectric is first formed and later removed and replaced with a hi-k dielectric prior to depositing the metal gate. In hi-k first process flows, the hi-k dielectric is deposited first and gate material is stripped off the hi-k dielectric and replaced with metal gate. The hi-k last process flows are more complicated than hi-k first process flows. They require more masking steps but avoid exposing the hi-k dielectric to chemicals that may degrade the hi-k dielectric. Replacement gate process flows are more complicated than gate first process flows but allow more flexibility in setting the work functions of the transistors.